High speed ADCs have become quite inexpensive and are commonly deployed. Care needs to be done when analyzing their outputs to determine sources of noise. Whereas noise at the input can often be averaged out, a noisy reference can cause “flat” sections in the transfer function where a change in the input does not produce the expected changes in the output.
Successive Approximation ADC operation:
There are a couple of different variations for the successive approximation ADC, with the basic version converting one bit at a time, starting with the most significant bit, working towards the least. In the case of a 16-bit converter, one design style will use a 16-bit DAC, with its output first set to half scale to compare against the sampled input. If the DAC output is higher than the sampled input, the MSB will be set in the result, if not it will be cleared. The next lower bit is then set high in addition to current result bit pattern. Again, the comparator is checked to see if the DAC result is higher or lower than the sampled input, with the tested bit saved as high if the comparator shows the input higher than the current estimate, and the bit cleared if it is lower. This repeats until all 16 bits have been resolved.
The input for this example was 2.12v, with 3.3v being the full-scale reference; only 6 bits are shown for brevity. The nearest resolved value is 2.114v, which was achieved an error of .006v
There multiple alternative ADC structures, such as using capacitive ladders to capture the input. This design then compares to half scale of the reference. If the comparator shows the input to be higher, half of the reference is subtracted from the stored value and the bit being tested is set high; if not, the bit being tested is set to 0 and nothing is subtracted from the stored input value. The resulting analog value is then multiplied by two, and the process repeats for each of the successive bits. The noise issues shown affect the various successive approximation designs.
This conversion process seems straight forward, but it assumes the reference is stable for all of the decisions made along the way. If there is noise in the reference, or sag when sampled, this can result in a bad decision being made at one of the decision points. If any particular bit that should have been a zero is falsely forced to be a one due to noise, the test value will be high for the succeeding tests resulting in them having zero values. A similar prospect happens if a bit is wrongly selected as a zero, except that now all the trailing digits below the erroneous bit will then be ones. In the tables and graphs below, Bit 3 was corrupted, reporting as a zero instead of a one. All the successive bits are thus forced to ones trying to reduce the error for each of the successive tests. The final error remains significant: For an input of 2.12v, the measurement was 2.011v, .109v of error in this example.
If the input had been 2.4v with the same bit testing wrong, the same 2.0109 volts would have been reported, this time with an error of .389v, making the 6-bit ADC only good to 3 bits!
The result is that the effective resolution of the ADC is less than the rating of the part. A 16-bit converter may act more like a 12-bit converter. If you really need the full resolution of the ADC, such distortion of the output can significantly affect the data. Unlike a nice gaussian noise at the input, this type of error does not average out nicely, as varying ranges of the input can be forced to a single output value.
How to Locate Preferred Values in the Data:
These preferred values can be located by applying either a ramp or a gaussian noise signal, or even your standard measurement signal (if it smoothly covers enough of the range) into the ADC.
Using a spread sheet to mask off most significant bits, leaving the lower (typically) 5 bits for analysis. The relative frequency for each of the 32 combinations (5 bits) are counted in the data. If the signal is varying over a range at least several times larger than would be represented by 32 counts (so multiple passes over each of the bins is present), and preferably it would evenly cover most of the range of the ADC (reduce the input range if saturated values are found in the data), the occurrence of each of the 32 values, 0 to 31, should be fairly equal resulting in a flat distribution curve.
The random distribution (using rand in the spread sheet) of some 100,000 points shows the resulting variation. The counts were normalized to the expected occurrence rate of each pattern. As expected, they are close to expected relative frequency (1), though some random variation is expected.
The following data were measured in a system with a noisy reference. Again, the counts have been normalized to the expected occurrence rates. It can be easily seen that values with trailing ones are over-represented in the data: 3, 7, 11, 15, 19, 23, 27, 31 – almost 83% of the data for only 25% of the values. Those with trailing zeros: 4, 8, 12, 16, 20, 24, 28 have less than .2% of the data – almost completely missing - and the remaining values are also significantly suppressed. The effective number of bits of this ADC has been significantly reduced. This distortion can greatly affect the resulting data when it is further processed!
This problem can be eliminated by reducing electrical noise at the ADC power supply, proper analog ground practices, keeping digital noise out of the analog section, driving the ADC with properly conditioned signals, and using a low impedance, stable, and well bypassed reference. Proper application allows you to use the ADC up to its full rated specification.
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Editor’s Note: Say hello to Don Labriola of QuickSilver Controls (quicksilvercontrols.com), our newest motors blogger for Power Transmission Engineering magazine. Don’s postings will appear at various times throughout the year. He joins George Holling of Rocky Mountain Technologies (rockymountaintechnologies.com), representing a team of respected experts in their field of the latest motor and motion control technology.